Sindbad~EG File Manager
ELF (�4 4 � � (� (�s s � 8 8 CFGL � � 0D � # default_process-pakala-1.0-adsp.dtb �E � # charger_process-pakala-1.0-adsp.dtb �N � � ! audio_process-pakala-1.0-adsp.dtb �] h � qsh_process-pakala-1.0-adsp.dtb $j � � ois_process-pakala-1.0-adsp.dtb �r H � 0 default_process-pakala-qrd-1.0-adsp-overlay.dtbo�
�� D0 8 � ( A� l qcom,pakala qcom,pakala aliases ,/soc/spmi_bus@c400000 6/soc/spmi_bus@c431000 soc @ O clock-controller@100000 qcom,gcc-pakala qcom,cc-pakala � H 0 @ P ` p � � � � � / B / B � LGCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ7_200_CL36L12_LE GCC_RPU_XPU4 V @ � clock-controller@1f40000 ( qcom,lpass_aon_cc-pakala qcom,cc-pakala P H� � � � �� � �` �p � &� 4 LTCSR_TCSR_REGS LPASS_QDSP6SS_PUB LPASS_QDSP6SS_QDSP6SS_QDSP6SSV79_CORE_CC_SWI LPASS_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON LPASS_QDSP6SS_QDSP6SSV79_CORE_CC_REG LPASS_AON_CC_PLL_CM_PLL_TAYCAN_COMMON LPASS_AON_CC_AHB2PHY_SWMAN LPASS_AON_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_CC_LPASS_AON_CC_REG LPASS_LPI_TCM_REG V @ P clock-controller@7700000 + qcom,lpass_aon_mx_cc-pakala qcom,cc-pakala Hp p` pp p� � � LLPASS_AON_MX_CC_RO_PLL_CM_PLL_PONGO_COMMON LPASS_AON_MX_CC_AHB2PHY_SWMAN LPASS_AON_MX_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_MX_CC_LPASS_AON_MX_CC_REG V @ Q clock-controller@6bc0000 * qcom,lpass_audio_cc-pakala qcom,cc-pakala 0 H� � � �` �p �� � LLPASS_AUDIO_CC_PLL_CM_PLL_ZONDA_COMMON LPASS_AUDIO_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_AUDIO_CC_LCC_PLL_CM_PLL_JBIST4_COMMON LPASS_AUDIO_CC_AHB2PHY_SWMAN LPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AUDIO_CC_LPASS_AUDIO_CC_REG V @ R clock-controller@7b00000 ) qcom,lpass_core_cc-pakala qcom,cc-pakala 0 H� �` �p �� � 0 � � LLPASS_LPASS_CORE_CC_DIG_PLL_LPASS_CORE_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_LPASS_CORE_CC_REG LPASS_HW_AF_CORE LPASS_CORE_GDSC V @ S clock-controller@6e40000 * qcom,lpass_lpmla_cc-pakala qcom,cc-pakala H� �` �p � @ � LLPASS_LPMLA_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPMLA_CC_AHB2PHY_SWMAN LPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPMLA_CC_LPASS_LPMLA_CC_REG V @ T clock-controller@7a00000 qcom,scc-pakala qcom,cc-pakala H� LSSC_SCC_SCC_SCC_REG V @ } cesta@7213000 ' qcom,lpass_cesta-pakala qcom,cc-pakala ( H!0 !4 !8 !X !_ @ LLPASS_CRMB LPASS_CRMB_PT LPASS_CRMC LPASS_CRMV LPASS_CRM_COMMON @ U glink qcom,glink proc-info c xport-smem-config edge-01 h t @ ~ � � N edge-02 h t @ ~ � � N edge-03 h t @ ~ � � N xport-qmp-config edge-01 �aop_adsp �rpm h �� � � � � � ipc_router qcom,ipc_router proc-info adsp ! devcfg-glink-xals edge-01 $SMEM �apss .IPCRTR 6 >� G R � � � edge-02 $SMEM �mpss .IPCRTR 6 >� G R � � � devcfg-mhi-xals edge-01 $MHI �wpss Z 2 e 3 smp2p qcom,smp2p proc-info adsp p x smp2p-interrupts intr-01 � � � intr-02 � � � smem
qcom,smem
�CORE_TOP_CSR �� � 0 �
@
@ pinctrl@f100000 ! qcom,pakala-pinctrl qcom,pinctrl H � � � � ! � � � @ V qup2_se0_l0 @ ! ibi_i3c_qup2_se0_sda @ W qup2_se0_l1 @ " ibi_i3c_qup2_se0_scl @ X qup2_se0_l2 @ # qup2_se0_l3 @ $ qup2_se1_l0 @ % ibi_i3c_qup2_se1_sda @ Y qup2_se1_l1 @ & ibi_i3c_qup2_se1_scl @ Z qup2_se1_l2 @ ' qup2_se1_l3 @ ( qup2_se2_l0 @ ) ibi_i3c_qup2_se2_sda @ [ qup2_se2_l1 @ * ibi_i3c_qup2_se2_scl @ \ qup2_se2_l2
@ + qup2_se3_l0 @ - ibi_i3c_qup2_se3_sda @ ] qup2_se2_l6 @ ^ qup2_se3_l1
@ . ibi_i3c_qup2_se3_scl
@ _ qup2_se2_l4
@ ` qup2_se3_l2 @ / qup2_se2_l3 @ , qup2_se3_l3 @ 0 qup2_se2_l5 @ a qup2_se4_l0 @ 1 qup2_se4_l1 @ 2 qup2_se4_l2 @ 3 qup2_se4_l3 @ 4 qup2_se5_l0 @ 5 qup2_se5_l1 @ 6 qup2_se5_l2 @ 7 qup2_se5_l3 @ 8 qup2_se5_l6 @ b qup2_se6_l0 @ 9 qup2_se6_l1 @ : qup2_se6_l2 @ ; qup2_se6_l3 @ < qup2_se7_l0 @ = ibi_i3c_qup2_se7_sda @ c qup2_se7_l1 @ > ibi_i3c_qup2_se7_scl @ d qup2_se7_l2 @ ? qup2_se7_l3 @ @ qup1_se0_l0 @ ibi_i3c_qup1_se0_sda @ e qup1_se0_l1 ! @ ibi_i3c_qup1_se0_scl ! @ f qup1_se0_l2 " @ qup1_se0_l3 # @ qup1_se1_l0 $ @ ibi_i3c_qup1_se1_sda $ @ g qup1_se1_l1 % @ ibi_i3c_qup1_se1_scl % @ h qup1_se1_l2 & @ qup1_se1_l3 ' @ qup1_se2_l0 ( @ qup1_se2_l1 ) @
qup1_se2_l2 * @ qup1_se2_l3 + @ qup1_se3_l0 , @
qup1_se3_l1 - @ qup1_se3_l2 . @ qup1_se3_l3 / @ qup1_se4_l0 0 @ ibi_i3c_qup1_se4_sda 0 @ i qup1_se4_l1 1 @ ibi_i3c_qup1_se4_scl 1 @ j qup1_se4_l2 2 @ qup1_se4_l3 3 @ qup1_se5_l0 4 @ qup1_se5_l1 5 @ qup1_se5_l2 6 @ qup1_se5_l3 7 @ qup1_se6_l0 8 @ qup1_se6_l1 9 @ qup1_se6_l2 : @ qup1_se6_l3 ; @ qup1_se7_l0 < @ qup1_se7_l1 = @ qup1_se7_l2 > @ qup1_se7_l3 ? @ qup1_se2_l4 � @ k qup1_se2_l5 � @ l qup1_se2_l6 � @ m top_qup1_se0_i2c_active �
�
@ � top_qup1_se0_i2c_sleep � � @ � top_qup1_se0_spi_active X X X X @ � top_qup1_se0_spi_sleep � ! � ! � ! � ! @ � top_qup1_se0_uart_active � � � � @ � top_qup1_se0_uart_sleep � � � � @ � top_qup1_se1_i2c_active �
�
@ � top_qup1_se1_i2c_sleep � � @ � top_qup1_se1_spi_active X X X X @ � top_qup1_se1_spi_sleep � ! � ! � ! � ! @ � top_qup1_se1_uart_active � � � � @ � top_qup1_se1_uart_sleep � � � � @ � top_qup1_se2_i2c_active �
�
@ � top_qup1_se2_i2c_sleep �
� @ � top_qup1_se2_spi_active X
X X X @ � top_qup1_se2_spi_sleep � !
� ! � ! � ! @ � top_qup1_se2_uart_active �
� � � @ � top_qup1_se2_uart_sleep �
� � � @ � top_qup1_se3_i2c_active
�
�
@ � top_qup1_se3_i2c_sleep
� � @ top_qup1_se3_spi_active
X X X X @ top_qup1_se3_spi_sleep
� ! � ! � ! � ! @ top_qup1_se3_uart_active
� � � � @ top_qup1_se3_uart_sleep
� � � � @ top_qup1_se4_i2c_active �
�
@ top_qup1_se4_i2c_sleep � � @ top_qup1_se4_spi_active X X X X @ top_qup1_se4_spi_sleep � ! � ! � ! � ! @ top_qup1_se4_uart_active � � � � @ top_qup1_se4_uart_sleep � � � � @
top_qup1_se5_i2c_active �
�
@ top_qup1_se5_i2c_sleep � � @ top_qup1_se5_spi_active X X X X @
top_qup1_se5_spi_sleep � ! � ! � ! � ! @ top_qup1_se5_uart_active � � � � @ top_qup1_se5_uart_sleep � � � � @ top_qup1_se6_i2c_active �
�
@ top_qup1_se6_i2c_sleep � � @ top_qup1_se6_spi_active X X X X @ top_qup1_se6_spi_sleep � ! � ! � ! � ! @ top_qup1_se6_uart_active � � � � @ top_qup1_se6_uart_sleep � � � � @ top_qup1_se7_i2c_active �
�
@ top_qup1_se7_i2c_sleep � � @ top_qup1_se7_spi_active X X X X @ top_qup1_se7_spi_sleep � ! � ! � ! � ! @ top_qup1_se7_uart_active � � � � @ top_qup1_se7_uart_sleep � � � � @ top_qup2_se0_i2c_active ! �
" �
@ top_qup2_se0_i2c_sleep ! � " � @ top_qup2_se0_spi_active !X "X #X $X @ top_qup2_se0_spi_sleep ! � ! " � ! # � ! $ � ! @ top_qup2_se0_uart_active ! � " � # � $ � @ ! top_qup2_se0_uart_sleep ! � " � # � $ � @ " top_qup2_se1_i2c_active % �
& �
@ # top_qup2_se1_i2c_sleep % � & � @ $ top_qup2_se1_spi_active %X &X 'X (X @ % top_qup2_se1_spi_sleep % � ! & � ! ' � ! ( � ! @ & top_qup2_se1_uart_active % � & � ' � ( � @ ' top_qup2_se1_uart_sleep % � & � ' � ( � @ ( top_qup2_se2_i2c_active ) �
* �
@ ) top_qup2_se2_i2c_sleep ) � * � @ * top_qup2_se2_spi_active )X *X +X ,X @ + top_qup2_se2_spi_sleep ) � ! * � ! + � ! , � ! @ , top_qup2_se2_uart_active ) � * � + � , � @ - top_qup2_se2_uart_sleep ) � * � + � , � @ . top_qup2_se3_i2c_active - �
. �
@ / top_qup2_se3_i2c_sleep - � . � @ 0 top_qup2_se3_spi_active -X .X /X 0X @ 1 top_qup2_se3_spi_sleep - � ! . � ! / � ! 0 � ! @ 2 top_qup2_se3_uart_active - � . � / � 0 � @ 3 top_qup2_se3_uart_sleep - � . � / � 0 � @ 4 top_qup2_se4_i2c_active 1 �
2 �
@ 5 top_qup2_se4_i2c_sleep 1 � 2 � @ 6 top_qup2_se4_spi_active 1X 2X 3X 4X @ 7 top_qup2_se4_spi_sleep 1 � ! 2 � ! 3 � ! 4 � ! @ 8 top_qup2_se4_uart_active 1 � 2 � 3 � 4 � @ 9 top_qup2_se4_uart_sleep 1 � 2 � 3 � 4 � @ : top_qup2_se5_i2c_active 5 �
6 �
@ ; top_qup2_se5_i2c_sleep 5 � 6 � @ < top_qup2_se5_spi_active 5X 6X 7X 8X @ = top_qup2_se5_spi_sleep 5 � ! 6 � ! 7 � ! 8 � ! @ > top_qup2_se5_uart_active 5 � 6 � 7 � 8 � @ ? top_qup2_se5_uart_sleep 5 � 6 � 7 � 8 � @ @ top_qup2_se6_i2c_active 9 �
: �
@ A top_qup2_se6_i2c_sleep 9 � : � @ B top_qup2_se6_spi_active 9X :X ;X <X @ C top_qup2_se6_spi_sleep 9 � ! : � ! ; � ! < � ! @ D top_qup2_se6_uart_active 9 � : � ; � < � @ E top_qup2_se6_uart_sleep 9 � : � ; � < � @ F top_qup2_se7_i2c_active = �
> �
@ G top_qup2_se7_i2c_sleep = � > � @ H top_qup2_se7_spi_active =X >X ?X @X @ I top_qup2_se7_spi_sleep = � ! > � ! ? � ! @ � ! @ J top_qup2_se7_uart_active = � > � ? � @ � @ K top_qup2_se7_uart_sleep = � > � ? � @ � @ L pinctrl@7760000 ! qcom,pakala-pinctrl qcom,pinctrl Hv � � ! � \ E E E E E E E E E E E E E E E E E E E E E E E @ n slimbus_clk @ A slimbus_data @ B slimbus_default_gpio_cfg A � ! B� ! @ M pinctrl@75C0000 ! qcom,pakala-pinctrl qcom,pinctrl H\ � - � ! � � � a a E E a a a a a a E E E E I E Q Q E E Q Q Q Q E E E E E E E E E E E E E E E E E E E E E @ o ssc_qupv3_se0_0 @ C ssc_qupv3_se0_1 @ D ssc_qupv3_se1_0 @ E ssc_qupv3_se1_1 @ F ssc_qupv3_se2_0 @ I ssc_qupv3_se2_1 @ J ssc_qupv3_se2_2 @ K ssc_qupv3_se4_4 @ p ssc_qupv3_se2_3 @ L ssc_qupv3_se4_5 @ q ssc_qupv3_se3_0 @ M ssc_qupv3_se2_4 @ r ssc_qupv3_se3_1 @ N ssc_qupv3_se2_5 @ s ssc_qupv3_se4_0
@ O ssc_qupv3_se4_1 @ P ssc_qupv3_se4_2 @ Q ssc_qupv3_se4_3
@ R ssc_qupv3_se5_2 @ U ssc_qupv3_se5_0 @ S ssc_qupv3_se1_2 @ G ssc_qupv3_se5_3 @ V ssc_qupv3_se5_1 @ T ssc_qupv3_se1_3 @ H ssc_qupv3_se6_0 @ W ssc_qupv3_se6_2 @ Y ssc_qupv3_se10_2 @ e ssc_qupv3_se6_1 @ X ssc_qupv3_se6_3 @ Z ssc_qupv3_se10_3 @ f ssc_qupv3_se7_2 @ ] ssc_qupv3_se7_0 @ [ ssc_qupv3_se7_3 @ ^ ssc_qupv3_se7_1 @ \ ssc_qupv3_se8_0 @ _ ssc_qupv3_se8_1 @ ` ssc_qupv3_se9_0 @ a ssc_qupv3_se9_1 @ b ssc_qupv3_se10_0 @ c ssc_qupv3_se10_1 @ d ssc_qupv3_se11_0 @ g ssc_qupv3_se11_1 @ h ssc_qupv3_se11_2 @ i ssc_qupv3_se11_3 @ j ssc_qupv3_se12_0 @ k ssc_qupv3_se12_1 @ l ssc_qupv3_se13_0 @ m ssc_qupv3_se13_1 ! @ n ssc_qupv3_se13_2 " @ o ssc_qupv3_se13_3 # @ p ssc_qupv3_se14_0 $ @ q ssc_qupv3_se14_1 % @ r qup_ssc0_i2c_active C �
D �
@ qup_ssc0_i2c_sleep C � D � @ � qup_ssc0_i3c_active C �
D �
@ � qup_ssc0_i3c_sleep C � ! D � ! @ � qup_ssc0_i3c_ibi_active C �
D �
@ � qup_ssc0_i3c_ibi_sleep C � ! D � ! @ � qup_ssc1_i2c_active E �
F �
@ � qup_ssc1_i2c_sleep E � F � @ � qup_ssc1_i3c_active E �
F �
@ � qup_ssc1_i3c_sleep E � ! F � ! @ � qup_ssc1_i3c_ibi_active E �
F �
@ � qup_ssc1_i3c_ibi_sleep E � ! F � ! @ � qup_ssc1_spi_active EX FX GX HX @ � qup_ssc1_spi_sleep E � ! F � ! G � ! H � ! @ � qup_ssc1_uart_active E � F � G � H � @ � qup_ssc1_uart_sleep E � F � G � H � @ � qup_ssc2_i2c_active I �
J �
@ � qup_ssc2_i2c_sleep I � J � @ � qup_ssc2_i3c_active I �
J �
@ � qup_ssc2_i3c_sleep I � ! J � ! @ � qup_ssc2_i3c_ibi_active I �
J �
@ � qup_ssc2_i3c_ibi_sleep I � ! J � ! @ � qup_ssc2_spi_active IX JX KX LX @ � qup_ssc2_spi_sleep I � ! J � ! K � ! L � ! @ � qup_ssc2_uart_active I � J � K � L � @ � qup_ssc2_uart_sleep I � J � K � L � @ � qup_ssc3_i2c_active M �
N �
@ � qup_ssc3_i2c_sleep M �! N �! @ � qup_ssc3_i3c_active M �
N �
@ � qup_ssc3_i3c_sleep M � ! N � ! @ � qup_ssc3_i3c_ibi_active M �
N �
@ � qup_ssc3_i3c_ibi_sleep M � ! N � ! @ � qup_ssc4_i2c_active O �
P �
@ � qup_ssc4_i2c_sleep O � P � @ � qup_ssc4_spi_active OX PX QX RX @ � qup_ssc4_spi_sleep O � ! P � ! Q � ! R � ! @ � qup_ssc4_uart_active O � P � Q � R � @ � qup_ssc4_uart_sleep O � P � Q � R � @ � qup_ssc5_i2c_active S �
T �
@ � qup_ssc5_i2c_sleep S � T � @ � qup_ssc5_i3c_active S �
T �
@ � qup_ssc5_i3c_sleep S � ! T � ! @ � qup_ssc5_i3c_ibi_active S �
T �
@ � qup_ssc5_i3c_ibi_sleep S � ! T � ! @ � qup_ssc5_uart_active S � T � U � V � @ � qup_ssc5_uart_sleep S � T � U � V � @ � qup_ssc6_i2c_active W �
X �
@ � qup_ssc6_i2c_sleep W � X � @ � qup_ssc6_i3c_active W �
X �
@ � qup_ssc6_i3c_sleep W � ! X � ! @ � qup_ssc6_i3c_ibi_active W �
X �
@ � qup_ssc6_i3c_ibi_sleep W � ! X � ! @ � qup_ssc6_uart_active W � X � Y � Z � @ � qup_ssc6_uart_sleep W � X � Y � Z � @ � qup_ssc7_i2c_active [ �
\ �
@ � qup_ssc7_i2c_sleep [ � \ � @ � qup_ssc7_uart_active [ � \ � ] � ^ � @ � qup_ssc7_uart_sleep [ � \ � ] � ^ � @ � qup_ssc8_i2c_active _ �
` �
@ � qup_ssc8_i2c_sleep _ � ` � @ � qup_ssc8_i3c_active _ �
` �
@ � qup_ssc8_i3c_sleep _ � ! ` � ! @ � qup_ssc8_i3c_ibi_active _ �
` �
@ � qup_ssc8_i3c_ibi_sleep _ � ! ` � ! @ � qup_ssc9_i2c_active a �
b �
@ � qup_ssc9_i2c_sleep a � b � @ � qup_ssc9_i3c_active a �
b �
@ � qup_ssc9_i3c_sleep a � ! b � ! @ � qup_ssc9_i3c_ibi_active a �
b �
@ � qup_ssc9_i3c_ibi_sleep a � ! b � ! @ � qup_ssc10_i2c_active c �
d �
@ � qup_ssc10_i2c_sleep c � d � @ � qup_ssc10_spi_active cX dX eX fX @ � qup_ssc10_spi_sleep c � ! d � ! e � ! f � ! @ � qup_ssc10_uart_active c � d � e � f � @ � qup_ssc10_uart_sleep c � d � e � f � @ � qup_ssc11_i2c_active g �
h �
@ � qup_ssc11_i2c_sleep g � h � @ � qup_ssc11_spi_active gX hX iX jX @ � qup_ssc11_spi_sleep g � ! h � ! i � ! j � ! @ � qup_ssc11_uart_active g � h � i � j � @ � qup_ssc11_uart_sleep g � h � i � j � @ � qup_ssc12_i2c_active k �
l �
@ � qup_ssc12_i2c_sleep k � l � @ � qup_ssc13_i2c_active m �
n �
@ � qup_ssc13_i2c_sleep m � n � @ � qup_ssc13_i3c_active m �
n �
@ � qup_ssc13_i3c_sleep m � ! n � ! @ � qup_ssc13_i3c_ibi_active m �
n �
@ � qup_ssc13_i3c_ibi_sleep m � ! n � ! @ � qup_ssc13_spi_active mX nX oX pX @ � qup_ssc13_spi_sleep m � ! n � ! o � ! p � ! @ � qup_ssc13_uart_active m � n � o � p � @ � qup_ssc13_uart_sleep m � n � o � p � @ � qup_ssc14_i2c_active q �
r �
@ � qup_ssc14_i2c_sleep q � r � @ � qup_ssc14_i3c_active q �
r �
@ � qup_ssc14_i3c_sleep q � ! r � ! @ � qup_ssc14_i3c_ibi_active q �
r �
@ � qup_ssc14_i3c_ibi_sleep q � ! r � ! @ � timetick timer@68a2000 qcom,timetick H� )SystemTimer 4$� ? I @ t timer@68a3000 qcom,timetick H�0 )WakeUpTimer 4$� ? I @ u spmi_bus@c400000 qcom,spmi-pmic-arb H @ P pmk8550@0 qcom,spmi-pmic H � @ v spmi-vadc@92 qcom,spmi-vadc H � Y g k o t x s vadc_ch_cfg VPH_PWR �VPH_PWR � � � � � � � � � � � VBATT �VBATT � � � � � � � � � � � VBATT_2S �VBATT_2S � � � � � � � � � � � VBATT_2S_MID
�VBATT_2S_MID � � � � � � � � � � � CHG_TEMP �CHG_TEMP � � � � � � � � � � � BATT_THERM �BATT_THERM � D � � � � � ����� � � �� � � BATT_THERM_PU_10K �BATT_THERM_PU_10K � $ � � � � � ����� � � ' � � BATT_THERM_PU_400K �BATT_THERM_PU_400K � d � � � � � ����� � � � � � BATT_ID_OHMS
�BATT_ID_OHMS � E � � � � � � � � �� � BATT_ID_OHMS_PU_10K �BATT_ID_OHMS_PU_10K � % � � � � � � � � ' � BATT_ID_OHMS_PU_400K �BATT_ID_OHMS_PU_400K � e � � � � � � � � � � CONN_THERM_PM_07 �CONN_THERM_PM_07 � G � � � � � ����� � � �� � � USB_SNS_V_MV
�USB_SNS_V_MV � � � � � � � � � � USB_IN_I_MA_PM_07 �USB_IN_I_MA_PM_07 � � � � � � � � � � � VIN_MUX �VIN_MUX � � � � � � � � � � IBATT_MA �IBATT_MA � � � � � � � � � � � � IBATT2_MA
�IBATT2_MA � � � � � � � � � � � � BATT2_THERM �BATT2_THERM � L � � � � � ����� � � �� � � BATT2_THERM_PU_10K �BATT2_THERM_PU_10K � , � � � � � ����� � � ' � � BATT2_THERM_PU_400K �BATT2_THERM_PU_400K � l � � � � � ����� � � � � � BATT2_ID_OHMS �BATT2_ID_OHMS � K � � � � � � � � �� � BATT2_ID_OHMS_PU_10K �BATT2_ID_OHMS_PU_10K � + � � � � � � � � ' � BATT2_ID_OHMS_PU_400K �BATT2_ID_OHMS_PU_400K � k � � � � � � � � � � USBC_MUX_OPEN �USBC_MUX_OPEN � � � � � � � � � � USBC_MUX_10K
�USBC_MUX_10K � 3 � � � � � � � � ' � USBC_MUX_100K �USBC_MUX_100K � S � � � � � � � � �� � USBC_MUX_400K �USBC_MUX_400K � s � � � � � � � � � � WLS_THERM
�WLS_THERM � M � � � � � ����� � � �� � � ICHG_SMB_SMB_A �ICHG_SMB_SMB_A � � � � � � ( ) � � � � � ICHG_SMB_SMB_B �ICHG_SMB_SMB_B � � � � � � ( ) � � � � � IIN_SMB_SMB_A �IIN_SMB_SMB_A � � � � � � ( ) � � � � � IIN_SMB_SMB_B �IIN_SMB_SMB_B � � � � � � ( ) � � � � � SMB_TEMP_I_SMB_A �SMB_TEMP_I_SMB_A � � � � � � � � � � � SMB_TEMP_I_SMB_B �SMB_TEMP_I_SMB_B � � � � � � � � � � � vadc-avg-ch gpio-map sid7_amux4_gpio � � sid7_amux2_gpio � � sid7_amux3_gpio � � therm_table @ s therm_tb1 � � @�x � -�� � �$ � �� � R� � Ȩ �� (l m %� 1� z� � % �� * 5` / �� 4 � 9 �� > �� C i� H V� M G| R ;` W 18 \ )h a "� f L k � p " u z �
\ � � �
� therm_tb2 � X � �$ @ 8 �( ѐ �H jL *h � x� �4 ƨ
0� �
�` b� \� � � �( �� MH vadc_ibatt_tb � �������� N N usbin_i_tb � � S � chg_temp_tb � � ��ŀ S p� smb_itemp_tb � � ��$� S + smb_vtemp_tb � � ��� S I ichg_fb_tb � �������9 S -� vadctm_meas_cfg � VPH_PWR �VPH_PWR � � �� � � � � ' VBATT �VBATT � � �� � � � � � VBATT_2S �VBATT_2S � � �� � � � � ' pm8550@1 qcom,spmi-pmic H � pm8550ve@3 qcom,spmi-pmic H � luminous@4 qcom,spmi-pmic H � pm8550vs@5 qcom,spmi-pmic H � pm8550ve@6 qcom,spmi-pmic H � pm8750bh@7 qcom,spmi-pmic H � pm8550ve@8 qcom,spmi-pmic H � pm8550vs@9 qcom,spmi-pmic H � pmr735d@a qcom,spmi-pmic H
� pm8010@c qcom,spmi-pmic H � pm8010@d qcom,spmi-pmic H
� spmi_bus@c431000 qcom,spmi-pmic-arb H C P cxstmtrace@37000000 qcom,stmtrace H7 ) 3 lpistmtrace@7100000 qcom,stmtrace H ) 3 @ cxstmcfg@10002000 qcom,stmcfg H = B � lpistmcfg@10B43000 qcom,stmcfg H�0 = B � cxetb@10B05000 qcom,tmc H�P lpietb@10B45000 qcom,tmc H�P qdss N t Y i u t r v v t w v t � w v t � w v t � w v t � v t � v t � v t � v t � v t � t 0 � � � L� � L � !_!_ � % 2 funnel@10041000
qcom,tfunnel H @ u funnel@10B04000
qcom,tfunnel H�@ @ t funnel@10B44000
qcom,tfunnel H�@ @ v funnel@10B50000
qcom,tfunnel H� @ w tpdm@10B46000
qcom,tpdm H�` ?lpass � x I S tpdm@10B52000
qcom,tpdm H� ?lpi_rscc � y I S [ tpdm@10B54000
qcom,tpdm H�@
?lpi_audio � z I S tpdm@10B34000
qcom,tpdm H�@ ?ddr_lpi � { I S tpda@10B47000
qcom,tpda H�p
dlpass-lpi = n �port_lpi_tpda @ x tpda@10B53000
qcom,tpda H�0 dlpass-rscc = 7 n �port_rscc_tpda @ y tpda@10B55000
qcom,tpda H�P dlpass-audio = 8 n �port_audio_tpda @ z tnoc@10B31000
qcom,tnoc � { H� = * B � �port_ddr_lpi_tnoc @ { cti@10B41000 qcom,cti �lpass_lpi_cti_1 H� cti@10B42000 qcom,cti �lpass_lpi_cti_sdc_2 H� cti@10B51000 qcom,cti �lpass_lpi_cti_3 H� cti@10B35000 qcom,cti �ddr_lpi_cti_0 H�P qdss_lpi_csr@6EE0000 qcom,qdss_lpi_csr H� kernel_test_devices@0 H � | interrupt-controller@10140000 test,interrupt-control H � � @ | device1@f101000 qcom,test,singleton �Device region mapping with name H !device1 Ltest_reg_singleton � ] �int1 device2@1011000 qcom,test,singleton ! �Device region mapping with index !device2 H � ^ �int2 device3@0 qcom,test,singleton �Device with no region mapping !device3 H � _ �int3 device4@1 qcom,test,not_compatible �Device not compatible !device4 H � `
�zero int4 device5@1010000 qcom,test,non_singleton �Device region mapping with name H !device5 Ltest_reg_non_singleton systemcache@24800000 qcom,systemcache @ H$� $� %� %� &� &� $ $` @ q Lllcc0_base llcc1_base llcc2_base llcc3_base llcc_bcast_or_base llcc_bcast_and_base ddrss_regs_base shrm_csr_base @ @ N llc-island qcom,llc-island islands island@c,ff800000 H �� | 6 ibi_ssc_0_cfg@7500000 qcom,ibi-controller HP ;�P J�P ` y g l G u ! } �ok @ ~ ibi_ssc_1_cfg@7510000 qcom,ibi-controller HQ ;�Q J�P ` y g l f u } �ok @ � ibi_ssc_2_cfg@7520000 qcom,ibi-controller HR ;�R J�P ` y g l � u } �ok @ � ibi_ssc_3_cfg@7530000 qcom,ibi-controller HS ;�S J�P ` y g l � u � } �ok @ � ibi_ssc_4_cfg@7540000 qcom,ibi-controller HT ;�T J�P ` y g l � u � } �ok @ � ibi_ssc_5_cfg@7550000 qcom,ibi-controller HU ;�U J�P ` y g l � u � } �ok @ � ibi_ssc_6_cfg@7560000 qcom,ibi-controller HV ;�V J�P ` y g l � u � } �ok @ � ibi_ssc_7_cfg@7570000 qcom,ibi-controller HW ;�W J�P ` y g l � u � } �ok @ � ibi_ssc_8_cfg@7580000 qcom,ibi-controller HX ;�X J�P ` y g l � u � } �ok @ � ibi_ssc_9_cfg@7590000 qcom,ibi-controller HY ;�Y J�P ` y g l � u � } �ok @ � gpi_gen_info � gpi_qup0 � � @ � � � gpi_qup1 ��p@ � [ @ � � � gpi_qup2 ��`@ � d @ � � � gpi_sscqup ��@ � @ � ! " # $ % & ' ( � � SSC_QUP_0@7900000 qcom,sscqup-controller H� �core2x core s-ahb m-ahb � }Sd� }d�4 }��v }�^�, � ;� �� �� ��р
�ok SSC_QUP_0_SE_0 qcom,se-controller ' ~ 0 9 B L� _ s } � �+ � � � � �se-clk � }H� J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � � � �disabled SSC_QUP_0_SE_1 qcom,se-controller @ ' � 0 9 B L� _ s } � �, � p � � �se-clk � } �Ǟ x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � � � ) � 3 � �disabled SSC_QUP_0_SE_2 qcom,se-controller � ' � 0 9 B L� _ s } � �- � @ � � � �se-clk � }~E: x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � � � ) � 3 � �disabled SSC_QUP_0_SE_3 qcom,se-controller � ' � 0 9 B L� _ s } � �. � B � � �se-clk � }� �w J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � � � � �disabled SSC_QUP_0_SE_4 qcom,se-controller ' 0 9 B L _ s } � �/ � � � � � �se-clk � }*̉ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � �disabled SSC_QUP_0_SE_5 qcom,se-controller @ ' � 0 9 B L� _ s } � �0 � E � � � �se-clk � }��� b �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep uart-default uart-sleep � � � � � � � � � � � � �disabled SSC_QUP_0_SE_6 qcom,se-controller � ' � 0 9 B L� _ s } � �1 � G � � � �se-clk � }�� b �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep uart-default uart-sleep � � � � � � � � � � � � �disabled SSC_QUP_0_SE_7 qcom,se-controller � ' 0 9 B L _ s } � �* � � � � � �se-clk � }�O�� . �i2c-default i2c-sleep uart-default uart-sleep � � � � � � � � �disabled SSC_QUP_0_SE_8 qcom,se-controller ' � 0 9 B L� _ s } � �) � � � �se-clk � }pP� J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � � � � �disabled SSC_QUP_0_SE_9 qcom,se-controller @ ' � 0 9 B L� _ s } � �� � � � �se-clk � }& J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � � � � �disabled SSC_QUP_0_SE_10 qcom,se-controller � ' 0 9
B L _ s } � �� � � � � �se-clk � }� �� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � �disabled SSC_QUP_0_SE_11 qcom,se-controller � ' 0 9 B L _ s } � �� � � � �se-clk � }l� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � �disabled SSC_QUP_0_SE_12 qcom,se-controller ' 0 9 B L� _ s } � �� � � � �se-clk � }��~ �i2c-default i2c-sleep � � � � �disabled SSC_QUP_0_SE_13 qcom,se-controller @ ' � 0 9
B L� _ s } � �� � � � �se-clk � }'*ɥ x �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � � � ) � 3 � �disabled SSC_QUP_0_SE_14 qcom,se-controller � ' � 0 9 B L� _ s } � �� � � � �se-clk � }�V�c J �i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep � � � � � � � � � � �disabled SSC_QUP_GPII_0_DATA = E � SSC_QUP_GPII_1_DATA = E � SSC_QUP_GPII_2_DATA = E � SSC_QUP_GPII_3_DATA = E � SSC_QUP_GPII_4_DATA = E � SSC_QUP_GPII_5_DATA = E � SSC_QUP_GPII_6_DATA = E � SSC_QUP_GPII_7_DATA = E � SSC_QUP_GPII_8_DATA = E � SSC_QUP_GPII_9_DATA = E � SSC_QUP_GPII_10_DATA =
E � SSC_QUP_GPII_11_DATA = E � SSC_QUP_GPII_12_DATA = E � SSC_QUP_GPII_13_DATA = E � SSC_QUP_GPII_14_DATA = E � TOP_QUP_1@a00000 qcom,qup-controller H � �core2x core s-ahb m-ahb � ��ۂ� �@��� �4(�~ �r�a� � ;�p ��| ��x ���
�ok TOP_QUP_1_SE_0 qcom,se-controller 0 0 9 B L _ s
} � � � � Q � �se-clk � � > D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � �disabled TOP_QUP_1_SE_1 qcom,se-controller @ 0 0 9 B L _ s } � � � � Q � �se-clk � �ދڬ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � �disabled TOP_QUP_1_SE_2 qcom,se-controller � 0 0 9 B L _ s
} � � � � Q � �se-clk � �E�4� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � � � � � � �disabled TOP_QUP_1_SE_3 qcom,se-controller � 0 0 9 B L _ s } � � � � Q � �se-clk � �l� � D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � � �disabled TOP_QUP_1_SE_4 qcom,se-controller 0 0 9 B L _ s
} � � � � Q � �se-clk � �*�KF D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � �
�disabled TOP_QUP_1_SE_5 qcom,se-controller @ 0 0 9 B L _ s } � � � � Q � �se-clk � �y� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � �
� �disabled TOP_QUP_1_SE_6 qcom,se-controller � 0 0 9 B L _ s
} � � � � Q � �se-clk � �o�&j D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � �ok TOP_QUP_1_SE_7 qcom,se-controller � 0 0 9 B L _ s
} � � � � Q � �se-clk � �G5� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � �disabled TOP_QUP_2@800000 qcom,qup-controller H � �core2x core s-ahb m-ahb � �p�i �_h� ��~t �0n�U � ;�` ��l ��h ���
�ok TOP_QUP_2_SE_0 qcom,se-controller 0 0 9 B L _ s
} � � � � Q � �se-clk � �b8� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � � � � ! " �disabled TOP_QUP_2_SE_1 qcom,se-controller @ 0 0 9 B L _ s } � � � � Q � �se-clk � ��'�� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � # � $ � % � & ' ( �disabled TOP_QUP_2_SE_2 qcom,se-controller � 0 0 9 B L _ s
} � � � � Q � �se-clk � ��+ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � ) � * � + � , - . �disabled TOP_QUP_2_SE_3 qcom,se-controller � 0 0 9 B L _ s } � � � � Q � �se-clk � ��,y D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � / � 0 � 1 � 2 3 4 �disabled TOP_QUP_2_SE_4 qcom,se-controller 0 0 9 B L _ s
} � � � � Q � �se-clk � �y��~ D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � 5 � 6 � 7 � 8 9 : �disabled TOP_QUP_2_SE_5 qcom,se-controller @ 0 0 9 B L _ s } � � � � Q � �se-clk � �w�� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � ; � < � = � > ? @ �disabled TOP_QUP_2_SE_6 qcom,se-controller � 0 0 9 B L _ s
} � � � � Q � �se-clk � �#,�� D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � A � B � C � D E F �disabled TOP_QUP_2_SE_7 qcom,i2c-controller � 0 0 9 B L _ s
} � � � � Q � �se-clk � ��r � D �i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep � G � H � I � J K L �disabled TOP_QUP_GPII_9_DATA = E � TOP_QUP_GPII_10_DATA =
E � ssc_qup_fw_cfg Y� b p�р } se0_cfg_qrd � ��P � � � � � } � � se1_cfg_qrd � @ ��Q � � � � � } � � se2_cfg_qrd � � ��R � � � � � } � � se3_cfg_qrd � � ��S � � � � � } � � se4_cfg_qrd � � � � � �� � } � � se5_cfg_qrd � @ ��T � � � � � } � � se6_cfg_qrd � � ��U � � � � � } � � se7_cfg_qrd � � � � � � �� � } � � se8_cfg_qrd �
��V � � � � � } � � se9_cfg_qrd �
@ ��W � � � � � } � � se10_cfg_qrd �
� � � � � �� � } � � se11_cfg_qrd �
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%7scc_smem_clk %? %H $� clock37 % J %# %+ %7lpass_aon_mx_cc_aad_clk %? %H $� busport-array busPort0 ) %Q %` %g %u %� busPort1 ) %Q @ %` %g %u %� busPort2 ) ? %Q @ %` %g %u � %� busPort3 ) @ %Q @ %` %g %u � %� busPort4 ) A %Q @ %` %g %u � %� busPort5 ) B %Q @ %` %g %u � %� busPort6 ) C %Q @ %` %g %u � %� busPort7 ) %Q %` %g %u � %� busPort8 ) %Q %` %g %u � %� busPort9 ) %Q %` %g %u � %� busPort10 ) %Q %` %g %u � %� busPort11 ) %Q @ %` %g %u � %� busPort12 ) %Q %` %g %u � %� busPort13 )
%Q %` %g %u � %� busPort14 ) %Q @ %` V %g %u � %� busPort15 ) %Q %` %g %u � %� busPort16 ) %Q @ %` %g %u 1 %� busPort17 ) %Q @ %` %g %u 1 %� busPort18 ) %Q %` %g %u � %� busPort19 ) %Q %` %g %u � %� busPort20 ) %Q %` %g %� %� $ busPort21 ) %Q %` %g %� %� $ busPort22 ) %Q %` %g %� %� $ busPort23 ) %Q %` %g %� %� $ busPort24 ) ! %Q %` %g %� %� $ busPort25 ) " %Q %` %g %� %� $ busPort26 ) $ %Q � %` %g %� %� $ busPort27 ) % %Q � %` %g %� � %� $ busPort28 ) ' %Q � %` %g %� ' %� $ busPort29 ) ( %Q � %` %g %� %� $ busPort30 ) + %Q %` %g %� %� $ busPort31 ) 1 %Q %` %g %� %� $ busPort32 ) 0 %Q %` %g %� %� $ busPort33 ) . %Q %` %g %� %� $ busPort34 ) 2 %Q %` %g %� %� $ busPort35 ) / %Q %` %g %� %� $ busPort36 ) 6 %Q %` %g B %� %� $ busPort37 ) 7 %Q %` %g C %� %� $ busPort38 ) 5 %Q %` d %g %� � %� 5 busPort39 ) = %Q %` %g %� %� = extroute-array extBusRoute0 %� %� % extBusRoute1 %� ? %� ( extBusRoute2 %� %� % extBusRoute3 %� @ %� ( extBusRoute4 %� %� % extBusRoute5 %� A %� ( extBusRoute6 %� %� % extBusRoute7 %� B %� ( extBusRoute8 %� %� % extBusRoute9 %� C %� ( mipsroute-array mipsBwRoute0 %� %� % mipsBwRoute1 %� ? %� ( pwrDomain-array pwrDomain0 $� %�/core/cpu/latency %� % %� %� %� pwrDomain1 $� ! %�lpass_core_cc_lpass_core_hm_gdsc %� % %� %� %� pwrDomain2 $� ! %�lpass_aon_cc_lpass_audio_hm_gdsc %� % %� %� %� pwrDomain3 $� %� %� % %� %� %� pwrDomain4 $� %�lpass_aon_cc_lpass_ssc_gdsc %� % %� %� %� pwrDomain5 $�
%�VaCore %� @ % %� %� %� features-array feature0 � %� � ` y feature1 � %� ` feature2 � %� ` feature3 � %� �� ` ��� feature4 � %� ` feature5 � %� ` feature6 � %� ` feature7 � %� ` feature8 � %� � ` ��� feature9 � %� ` ��� feature10 � %� 5�� ` ��� feature11 � %� /�� ` ��� feature12 � %� ` feature13 � %� � ` � feature14 � %� $=X ` ��� feature15 � %� �� ` '� feature16 � %� ` feature17 � %� ` feature18 � %� ` feature19 � %� ` feature20 � %� ` feature21 � %� ` feature22 � %� ` feature23 � %� ` feature24 � %� ` feature25 � %� ` feature26 � %� ` feature27 � %� ` feature28 � %� ` feature29 � %� ` ��� feature30 � %� ` feature31 � %� ` feature32 � %� ` feature33 � %� ` feature34 � %� ` feature35 � %� ` feature36 � %� ` feature37 � %� ` cestaBw-array client0 %� & &lpass path0 & &) 5 cestaClk-array clk0 % b %7lpass_aon_cc_sdc_proc_fclk_clk cestaPwrDomain-array pwrDomain0 $� %�lpass_aon_cc_lpass_ssc_gdsc config_arch qcom,config_arch compensatedDdrBwTable 0 &6 �� rp� � 0 &= �� ��� � 0 &D ܓ� ��� X 0 &K �t� �2� � 0 &R �U� �2� � 0 &Y &�6� �� � 0 &` ,�� s�� � 0 &g 2��� �� � 0 &n 8�ـ �� � 0 &u >��� �� � 0 &|������� �� � adspsnocVoteTable 8 &6 �� ��� � � ' 8 &= �� ��� � � ' 8 &D ܓ� ��� X X ' 8 &K �t� �2� � � ' 8 &R �U� e�� � � ' 8 &Y &�6� �O� � � ' 8 &` ,�� �� � � ' 8 &g 2��� �� � � ' 8 &n 8�ـ �U� � � ' 8 &u >��� *�� � � ' 8 &|������� ��� � � ' compensatedLecDdrBwTable 0 &6 �� ��� X 0 &= �� �2� � 0 &D � �� � 0 &K ׄ s�� � 0 &R �e �� � 0 &Y������� �� � adspLecsnocVoteTable 8 &6 �� ��� X 8 &= �� �2� � 8 &D � �O� � 8 &K ׄ �� � 8 &R �e �U� � 8 &Y������� ��� � compensatedMlDdrBwTable 0 &6 �� rp� X 0 &= kI� ��� � 0 &D Н� �2� � 0 &K 8� �� � 0 &R G�W s�� � 0 &Y �n! �� � 0 &`������� �� � adspMlsnocVoteTable 8 &6 �� ��� X 8 &= kI� ��� � 8 &D Н� �2� � 8 &K 8� �O� � 8 &R G�W �� � 8 &Y �n! �U� � 8 &`������� ��� � adspToLpiNocFreqTable &6 �0 $� &=$� 5 &D3� � &K=�P O� &RM�� j &YbkP $� mlToLpiNocFreqTable &6$� $� &=O� 5 &DRH � &K O� &R&�� j &Y0� $� systemcache qcom,systemcache-sw &� N &� @ &� # - . llc-lpi-dump qcom,llc-lpi-dump 4 &�QSH_ISLAND_POOL SSC_ISLAND_POOL QSHTECH_ISLAND_POOL __symbols__ 1/soc &�/soc/clock-controller@100000 &�/soc/clock-controller@1f40000 &�/soc/clock-controller@7700000 &�/soc/clock-controller@6bc0000 &�/soc/clock-controller@7b00000 &�/soc/clock-controller@6e40000 &�/soc/clock-controller@7a00000 &�/soc/cesta@7213000 ' /soc/pinctrl@f100000 ! '/soc/pinctrl@f100000/qup2_se0_l0 * ' /soc/pinctrl@f100000/ibi_i3c_qup2_se0_sda ! '1/soc/pinctrl@f100000/qup2_se0_l1 * '=/soc/pinctrl@f100000/ibi_i3c_qup2_se0_scl ! 'R/soc/pinctrl@f100000/qup2_se0_l2 ! '^/soc/pinctrl@f100000/qup2_se0_l3 ! 'j/soc/pinctrl@f100000/qup2_se1_l0 * 'v/soc/pinctrl@f100000/ibi_i3c_qup2_se1_sda ! '�/soc/pinctrl@f100000/qup2_se1_l1 * '�/soc/pinctrl@f100000/ibi_i3c_qup2_se1_scl ! '�/soc/pinctrl@f100000/qup2_se1_l2 ! '�/soc/pinctrl@f100000/qup2_se1_l3 ! '�/soc/pinctrl@f100000/qup2_se2_l0 * '�/soc/pinctrl@f100000/ibi_i3c_qup2_se2_sda ! '�/soc/pinctrl@f100000/qup2_se2_l1 * '�/soc/pinctrl@f100000/ibi_i3c_qup2_se2_scl ! (/soc/pinctrl@f100000/qup2_se2_l2 ! (/soc/pinctrl@f100000/qup2_se3_l0 * ( /soc/pinctrl@f100000/ibi_i3c_qup2_se3_sda ! (3/soc/pinctrl@f100000/qup2_se2_l6 ! (?/soc/pinctrl@f100000/qup2_se3_l1 * (K/soc/pinctrl@f100000/ibi_i3c_qup2_se3_scl ! (`/soc/pinctrl@f100000/qup2_se2_l4 ! (l/soc/pinctrl@f100000/qup2_se3_l2 ! (x/soc/pinctrl@f100000/qup2_se2_l3 ! (�/soc/pinctrl@f100000/qup2_se3_l3 ! (�/soc/pinctrl@f100000/qup2_se2_l5 ! (�/soc/pinctrl@f100000/qup2_se4_l0 ! (�/soc/pinctrl@f100000/qup2_se4_l1 ! (�/soc/pinctrl@f100000/qup2_se4_l2 ! (�/soc/pinctrl@f100000/qup2_se4_l3 ! (�/soc/pinctrl@f100000/qup2_se5_l0 ! (�/soc/pinctrl@f100000/qup2_se5_l1 ! (�/soc/pinctrl@f100000/qup2_se5_l2 ! (�/soc/pinctrl@f100000/qup2_se5_l3 ! (�/soc/pinctrl@f100000/qup2_se5_l6 ! )/soc/pinctrl@f100000/qup2_se6_l0 ! )/soc/pinctrl@f100000/qup2_se6_l1 ! ) /soc/pinctrl@f100000/qup2_se6_l2 ! ),/soc/pinctrl@f100000/qup2_se6_l3 ! )8/soc/pinctrl@f100000/qup2_se7_l0 * )D/soc/pinctrl@f100000/ibi_i3c_qup2_se7_sda ! )Y/soc/pinctrl@f100000/qup2_se7_l1 * )e/soc/pinctrl@f100000/ibi_i3c_qup2_se7_scl ! )z/soc/pinctrl@f100000/qup2_se7_l2 ! )�/soc/pinctrl@f100000/qup2_se7_l3 ! )�/soc/pinctrl@f100000/qup1_se0_l0 * )�/soc/pinctrl@f100000/ibi_i3c_qup1_se0_sda ! )�/soc/pinctrl@f100000/qup1_se0_l1 * )�/soc/pinctrl@f100000/ibi_i3c_qup1_se0_scl ! )�/soc/pinctrl@f100000/qup1_se0_l2 ! )�/soc/pinctrl@f100000/qup1_se0_l3 ! )�/soc/pinctrl@f100000/qup1_se1_l0 * )�/soc/pinctrl@f100000/ibi_i3c_qup1_se1_sda ! *
/soc/pinctrl@f100000/qup1_se1_l1 * */soc/pinctrl@f100000/ibi_i3c_qup1_se1_scl ! *./soc/pinctrl@f100000/qup1_se1_l2 ! *:/soc/pinctrl@f100000/qup1_se1_l3 ! *F/soc/pinctrl@f100000/qup1_se2_l0 ! *R/soc/pinctrl@f100000/qup1_se2_l1 ! *^/soc/pinctrl@f100000/qup1_se2_l2 ! *j/soc/pinctrl@f100000/qup1_se2_l3 ! *v/soc/pinctrl@f100000/qup1_se3_l0 ! *�/soc/pinctrl@f100000/qup1_se3_l1 ! *�/soc/pinctrl@f100000/qup1_se3_l2 ! *�/soc/pinctrl@f100000/qup1_se3_l3 ! *�/soc/pinctrl@f100000/qup1_se4_l0 * *�/soc/pinctrl@f100000/ibi_i3c_qup1_se4_sda ! *�/soc/pinctrl@f100000/qup1_se4_l1 * *�/soc/pinctrl@f100000/ibi_i3c_qup1_se4_scl ! *�/soc/pinctrl@f100000/qup1_se4_l2 ! *�/soc/pinctrl@f100000/qup1_se4_l3 ! + /soc/pinctrl@f100000/qup1_se5_l0 ! + /soc/pinctrl@f100000/qup1_se5_l1 ! +/soc/pinctrl@f100000/qup1_se5_l2 ! +$/soc/pinctrl@f100000/qup1_se5_l3 ! +0/soc/pinctrl@f100000/qup1_se6_l0 ! +</soc/pinctrl@f100000/qup1_se6_l1 ! +H/soc/pinctrl@f100000/qup1_se6_l2 ! +T/soc/pinctrl@f100000/qup1_se6_l3 ! +`/soc/pinctrl@f100000/qup1_se7_l0 ! +l/soc/pinctrl@f100000/qup1_se7_l1 ! +x/soc/pinctrl@f100000/qup1_se7_l2 ! +�/soc/pinctrl@f100000/qup1_se7_l3 ! +�/soc/pinctrl@f100000/qup1_se2_l4 ! +�/soc/pinctrl@f100000/qup1_se2_l5 ! +�/soc/pinctrl@f100000/qup1_se2_l6 - +�/soc/pinctrl@f100000/top_qup1_se0_i2c_active , +�/soc/pinctrl@f100000/top_qup1_se0_i2c_sleep - +�/soc/pinctrl@f100000/top_qup1_se0_spi_active , +�/soc/pinctrl@f100000/top_qup1_se0_spi_sleep . ,/soc/pinctrl@f100000/top_qup1_se0_uart_active - ,+/soc/pinctrl@f100000/top_qup1_se0_uart_sleep - ,C/soc/pinctrl@f100000/top_qup1_se1_i2c_active , ,[/soc/pinctrl@f100000/top_qup1_se1_i2c_sleep - ,r/soc/pinctrl@f100000/top_qup1_se1_spi_active , ,�/soc/pinctrl@f100000/top_qup1_se1_spi_sleep . ,�/soc/pinctrl@f100000/top_qup1_se1_uart_active - ,�/soc/pinctrl@f100000/top_qup1_se1_uart_sleep - ,�/soc/pinctrl@f100000/top_qup1_se2_i2c_active , ,�/soc/pinctrl@f100000/top_qup1_se2_i2c_sleep - -/soc/pinctrl@f100000/top_qup1_se2_spi_active , -/soc/pinctrl@f100000/top_qup1_se2_spi_sleep . -0/soc/pinctrl@f100000/top_qup1_se2_uart_active - -I/soc/pinctrl@f100000/top_qup1_se2_uart_sleep - -a/soc/pinctrl@f100000/top_qup1_se3_i2c_active , -y/soc/pinctrl@f100000/top_qup1_se3_i2c_sleep - -�/soc/pinctrl@f100000/top_qup1_se3_spi_active , -�/soc/pinctrl@f100000/top_qup1_se3_spi_sleep . -�/soc/pinctrl@f100000/top_qup1_se3_uart_active - -�/soc/pinctrl@f100000/top_qup1_se3_uart_sleep - -�/soc/pinctrl@f100000/top_qup1_se4_i2c_active , ./soc/pinctrl@f100000/top_qup1_se4_i2c_sleep - . /soc/pinctrl@f100000/top_qup1_se4_spi_active , .7/soc/pinctrl@f100000/top_qup1_se4_spi_sleep . .N/soc/pinctrl@f100000/top_qup1_se4_uart_active - .g/soc/pinctrl@f100000/top_qup1_se4_uart_sleep - ./soc/pinctrl@f100000/top_qup1_se5_i2c_active , .�/soc/pinctrl@f100000/top_qup1_se5_i2c_sleep - .�/soc/pinctrl@f100000/top_qup1_se5_spi_active , .�/soc/pinctrl@f100000/top_qup1_se5_spi_sleep . .�/soc/pinctrl@f100000/top_qup1_se5_uart_active - .�/soc/pinctrl@f100000/top_qup1_se5_uart_sleep - //soc/pinctrl@f100000/top_qup1_se6_i2c_active , /&/soc/pinctrl@f100000/top_qup1_se6_i2c_sleep - /=/soc/pinctrl@f100000/top_qup1_se6_spi_active , /U/soc/pinctrl@f100000/top_qup1_se6_spi_sleep . /l/soc/pinctrl@f100000/top_qup1_se6_uart_active - /�/soc/pinctrl@f100000/top_qup1_se6_uart_sleep - /�/soc/pinctrl@f100000/top_qup1_se7_i2c_active , /�/soc/pinctrl@f100000/top_qup1_se7_i2c_sleep - /�/soc/pinctrl@f100000/top_qup1_se7_spi_active , /�/soc/pinctrl@f100000/top_qup1_se7_spi_sleep . /�/soc/pinctrl@f100000/top_qup1_se7_uart_active - 0/soc/pinctrl@f100000/top_qup1_se7_uart_sleep - 0,/soc/pinctrl@f100000/top_qup2_se0_i2c_active , 0D/soc/pinctrl@f100000/top_qup2_se0_i2c_sleep - 0[/soc/pinctrl@f100000/top_qup2_se0_spi_active , 0s/soc/pinctrl@f100000/top_qup2_se0_spi_sleep . 0�/soc/pinctrl@f100000/top_qup2_se0_uart_active - 0�/soc/pinctrl@f100000/top_qup2_se0_uart_sleep - 0�/soc/pinctrl@f100000/top_qup2_se1_i2c_active , 0�/soc/pinctrl@f100000/top_qup2_se1_i2c_sleep - 0�/soc/pinctrl@f100000/top_qup2_se1_spi_active , 1/soc/pinctrl@f100000/top_qup2_se1_spi_sleep . 1/soc/pinctrl@f100000/top_qup2_se1_uart_active - 12/soc/pinctrl@f100000/top_qup2_se1_uart_sleep - 1J/soc/pinctrl@f100000/top_qup2_se2_i2c_active , 1b/soc/pinctrl@f100000/top_qup2_se2_i2c_sleep - 1y/soc/pinctrl@f100000/top_qup2_se2_spi_active , 1�/soc/pinctrl@f100000/top_qup2_se2_spi_sleep . 1�/soc/pinctrl@f100000/top_qup2_se2_uart_active - 1�/soc/pinctrl@f100000/top_qup2_se2_uart_sleep - 1�/soc/pinctrl@f100000/top_qup2_se3_i2c_active , 1�/soc/pinctrl@f100000/top_qup2_se3_i2c_sleep - 2/soc/pinctrl@f100000/top_qup2_se3_spi_active , 2 /soc/pinctrl@f100000/top_qup2_se3_spi_sleep . 27/soc/pinctrl@f100000/top_qup2_se3_uart_active - 2P/soc/pinctrl@f100000/top_qup2_se3_uart_sleep - 2h/soc/pinctrl@f100000/top_qup2_se4_i2c_active , 2�/soc/pinctrl@f100000/top_qup2_se4_i2c_sleep - 2�/soc/pinctrl@f100000/top_qup2_se4_spi_active , 2�/soc/pinctrl@f100000/top_qup2_se4_spi_sleep . 2�/soc/pinctrl@f100000/top_qup2_se4_uart_active - 2�/soc/pinctrl@f100000/top_qup2_se4_uart_sleep - 2�/soc/pinctrl@f100000/top_qup2_se5_i2c_active , 3/soc/pinctrl@f100000/top_qup2_se5_i2c_sleep - 3&/soc/pinctrl@f100000/top_qup2_se5_spi_active , 3>/soc/pinctrl@f100000/top_qup2_se5_spi_sleep . 3U/soc/pinctrl@f100000/top_qup2_se5_uart_active - 3n/soc/pinctrl@f100000/top_qup2_se5_uart_sleep - 3�/soc/pinctrl@f100000/top_qup2_se6_i2c_active , 3�/soc/pinctrl@f100000/top_qup2_se6_i2c_sleep - 3�/soc/pinctrl@f100000/top_qup2_se6_spi_active , 3�/soc/pinctrl@f100000/top_qup2_se6_spi_sleep . 3�/soc/pinctrl@f100000/top_qup2_se6_uart_active - 3�/soc/pinctrl@f100000/top_qup2_se6_uart_sleep - 4/soc/pinctrl@f100000/top_qup2_se7_i2c_active , 4-/soc/pinctrl@f100000/top_qup2_se7_i2c_sleep - 4D/soc/pinctrl@f100000/top_qup2_se7_spi_active , 4\/soc/pinctrl@f100000/top_qup2_se7_spi_sleep . 4s/soc/pinctrl@f100000/top_qup2_se7_uart_active - 4�/soc/pinctrl@f100000/top_qup2_se7_uart_sleep 4�/soc/pinctrl@7760000 ! 4�/soc/pinctrl@7760000/slimbus_clk " 4�/soc/pinctrl@7760000/slimbus_data . 4�/soc/pinctrl@7760000/slimbus_default_gpio_cfg 4�/soc/pinctrl@75C0000 % 4�/soc/pinctrl@75C0000/ssc_qupv3_se0_0 % 4�/soc/pinctrl@75C0000/ssc_qupv3_se0_1 % 5/soc/pinctrl@75C0000/ssc_qupv3_se1_0 % 5/soc/pinctrl@75C0000/ssc_qupv3_se1_1 % 5(/soc/pinctrl@75C0000/ssc_qupv3_se2_0 % 58/soc/pinctrl@75C0000/ssc_qupv3_se2_1 % 5H/soc/pinctrl@75C0000/ssc_qupv3_se2_2 % 5X/soc/pinctrl@75C0000/ssc_qupv3_se4_4 % 5h/soc/pinctrl@75C0000/ssc_qupv3_se2_3 % 5x/soc/pinctrl@75C0000/ssc_qupv3_se4_5 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se3_0 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se2_4 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se3_1 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se2_5 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se4_0 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se4_1 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se4_2 % 5�/soc/pinctrl@75C0000/ssc_qupv3_se4_3 % 6/soc/pinctrl@75C0000/ssc_qupv3_se5_2 % 6/soc/pinctrl@75C0000/ssc_qupv3_se5_0 % 6(/soc/pinctrl@75C0000/ssc_qupv3_se1_2 % 68/soc/pinctrl@75C0000/ssc_qupv3_se5_3 % 6H/soc/pinctrl@75C0000/ssc_qupv3_se5_1 % 6X/soc/pinctrl@75C0000/ssc_qupv3_se1_3 % 6h/soc/pinctrl@75C0000/ssc_qupv3_se6_0 % 6x/soc/pinctrl@75C0000/ssc_qupv3_se6_2 & 6�/soc/pinctrl@75C0000/ssc_qupv3_se10_2 % 6�/soc/pinctrl@75C0000/ssc_qupv3_se6_1 % 6�/soc/pinctrl@75C0000/ssc_qupv3_se6_3 & 6�/soc/pinctrl@75C0000/ssc_qupv3_se10_3 % 6�/soc/pinctrl@75C0000/ssc_qupv3_se7_2 % 6�/soc/pinctrl@75C0000/ssc_qupv3_se7_0 % 6�/soc/pinctrl@75C0000/ssc_qupv3_se7_3 % 6�/soc/pinctrl@75C0000/ssc_qupv3_se7_1 % 7
/soc/pinctrl@75C0000/ssc_qupv3_se8_0 % 7/soc/pinctrl@75C0000/ssc_qupv3_se8_1 % 7*/soc/pinctrl@75C0000/ssc_qupv3_se9_0 % 7:/soc/pinctrl@75C0000/ssc_qupv3_se9_1 & 7J/soc/pinctrl@75C0000/ssc_qupv3_se10_0 & 7[/soc/pinctrl@75C0000/ssc_qupv3_se10_1 & 7l/soc/pinctrl@75C0000/ssc_qupv3_se11_0 & 7}/soc/pinctrl@75C0000/ssc_qupv3_se11_1 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se11_2 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se11_3 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se12_0 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se12_1 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se13_0 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se13_1 & 7�/soc/pinctrl@75C0000/ssc_qupv3_se13_2 & 8/soc/pinctrl@75C0000/ssc_qupv3_se13_3 & 8/soc/pinctrl@75C0000/ssc_qupv3_se14_0 & 8'/soc/pinctrl@75C0000/ssc_qupv3_se14_1 ) 88/soc/pinctrl@75C0000/qup_ssc0_i2c_active ( 8L/soc/pinctrl@75C0000/qup_ssc0_i2c_sleep ) 8_/soc/pinctrl@75C0000/qup_ssc0_i3c_active ( 8s/soc/pinctrl@75C0000/qup_ssc0_i3c_sleep - 8�/soc/pinctrl@75C0000/qup_ssc0_i3c_ibi_active , 8�/soc/pinctrl@75C0000/qup_ssc0_i3c_ibi_sleep ) 8�/soc/pinctrl@75C0000/qup_ssc1_i2c_active ( 8�/soc/pinctrl@75C0000/qup_ssc1_i2c_sleep ) 8�/soc/pinctrl@75C0000/qup_ssc1_i3c_active ( 8�/soc/pinctrl@75C0000/qup_ssc1_i3c_sleep - 9/soc/pinctrl@75C0000/qup_ssc1_i3c_ibi_active , 9/soc/pinctrl@75C0000/qup_ssc1_i3c_ibi_sleep ) 92/soc/pinctrl@75C0000/qup_ssc1_spi_active ( 9F/soc/pinctrl@75C0000/qup_ssc1_spi_sleep * 9Y/soc/pinctrl@75C0000/qup_ssc1_uart_active ) 9n/soc/pinctrl@75C0000/qup_ssc1_uart_sleep ) 9�/soc/pinctrl@75C0000/qup_ssc2_i2c_active ( 9�/soc/pinctrl@75C0000/qup_ssc2_i2c_sleep ) 9�/soc/pinctrl@75C0000/qup_ssc2_i3c_active ( 9�/soc/pinctrl@75C0000/qup_ssc2_i3c_sleep - 9�/soc/pinctrl@75C0000/qup_ssc2_i3c_ibi_active , 9�/soc/pinctrl@75C0000/qup_ssc2_i3c_ibi_sleep ) 9�/soc/pinctrl@75C0000/qup_ssc2_spi_active ( :/soc/pinctrl@75C0000/qup_ssc2_spi_sleep * :&/soc/pinctrl@75C0000/qup_ssc2_uart_active ) :;/soc/pinctrl@75C0000/qup_ssc2_uart_sleep ) :O/soc/pinctrl@75C0000/qup_ssc3_i2c_active ( :c/soc/pinctrl@75C0000/qup_ssc3_i2c_sleep ) :v/soc/pinctrl@75C0000/qup_ssc3_i3c_active ( :�/soc/pinctrl@75C0000/qup_ssc3_i3c_sleep - :�/soc/pinctrl@75C0000/qup_ssc3_i3c_ibi_active , :�/soc/pinctrl@75C0000/qup_ssc3_i3c_ibi_sleep ) :�/soc/pinctrl@75C0000/qup_ssc4_i2c_active ( :�/soc/pinctrl@75C0000/qup_ssc4_i2c_sleep ) :�/soc/pinctrl@75C0000/qup_ssc4_spi_active ( ;/soc/pinctrl@75C0000/qup_ssc4_spi_sleep * ;/soc/pinctrl@75C0000/qup_ssc4_uart_active ) ;//soc/pinctrl@75C0000/qup_ssc4_uart_sleep ) ;C/soc/pinctrl@75C0000/qup_ssc5_i2c_active ( ;W/soc/pinctrl@75C0000/qup_ssc5_i2c_sleep ) ;j/soc/pinctrl@75C0000/qup_ssc5_i3c_active ( ;~/soc/pinctrl@75C0000/qup_ssc5_i3c_sleep - ;�/soc/pinctrl@75C0000/qup_ssc5_i3c_ibi_active , ;�/soc/pinctrl@75C0000/qup_ssc5_i3c_ibi_sleep * ;�/soc/pinctrl@75C0000/qup_ssc5_uart_active ) ;�/soc/pinctrl@75C0000/qup_ssc5_uart_sleep ) ;�/soc/pinctrl@75C0000/qup_ssc6_i2c_active ( ;�/soc/pinctrl@75C0000/qup_ssc6_i2c_sleep ) </soc/pinctrl@75C0000/qup_ssc6_i3c_active ( <$/soc/pinctrl@75C0000/qup_ssc6_i3c_sleep - <7/soc/pinctrl@75C0000/qup_ssc6_i3c_ibi_active , <O/soc/pinctrl@75C0000/qup_ssc6_i3c_ibi_sleep * <f/soc/pinctrl@75C0000/qup_ssc6_uart_active ) <{/soc/pinctrl@75C0000/qup_ssc6_uart_sleep ) <�/soc/pinctrl@75C0000/qup_ssc7_i2c_active ( <�/soc/pinctrl@75C0000/qup_ssc7_i2c_sleep * <�/soc/pinctrl@75C0000/qup_ssc7_uart_active ) <�/soc/pinctrl@75C0000/qup_ssc7_uart_sleep ) <�/soc/pinctrl@75C0000/qup_ssc8_i2c_active ( <�/soc/pinctrl@75C0000/qup_ssc8_i2c_sleep ) =/soc/pinctrl@75C0000/qup_ssc8_i3c_active ( =/soc/pinctrl@75C0000/qup_ssc8_i3c_sleep - =-/soc/pinctrl@75C0000/qup_ssc8_i3c_ibi_active , =E/soc/pinctrl@75C0000/qup_ssc8_i3c_ibi_sleep ) =\/soc/pinctrl@75C0000/qup_ssc9_i2c_active ( =p/soc/pinctrl@75C0000/qup_ssc9_i2c_sleep ) =�/soc/pinctrl@75C0000/qup_ssc9_i3c_active ( =�/soc/pinctrl@75C0000/qup_ssc9_i3c_sleep - =�/soc/pinctrl@75C0000/qup_ssc9_i3c_ibi_active , =�/soc/pinctrl@75C0000/qup_ssc9_i3c_ibi_sleep * =�/soc/pinctrl@75C0000/qup_ssc10_i2c_active ) =�/soc/pinctrl@75C0000/qup_ssc10_i2c_sleep * >/soc/pinctrl@75C0000/qup_ssc10_spi_active ) >/soc/pinctrl@75C0000/qup_ssc10_spi_sleep + >+/soc/pinctrl@75C0000/qup_ssc10_uart_active * >A/soc/pinctrl@75C0000/qup_ssc10_uart_sleep * >V/soc/pinctrl@75C0000/qup_ssc11_i2c_active ) >k/soc/pinctrl@75C0000/qup_ssc11_i2c_sleep * >/soc/pinctrl@75C0000/qup_ssc11_spi_active ) >�/soc/pinctrl@75C0000/qup_ssc11_spi_sleep + >�/soc/pinctrl@75C0000/qup_ssc11_uart_active * >�/soc/pinctrl@75C0000/qup_ssc11_uart_sleep * >�/soc/pinctrl@75C0000/qup_ssc12_i2c_active ) >�/soc/pinctrl@75C0000/qup_ssc12_i2c_sleep * >�/soc/pinctrl@75C0000/qup_ssc13_i2c_active ) ?/soc/pinctrl@75C0000/qup_ssc13_i2c_sleep * ?%/soc/pinctrl@75C0000/qup_ssc13_i3c_active ) ?:/soc/pinctrl@75C0000/qup_ssc13_i3c_sleep . ?N/soc/pinctrl@75C0000/qup_ssc13_i3c_ibi_active - ?g/soc/pinctrl@75C0000/qup_ssc13_i3c_ibi_sleep * ?/soc/pinctrl@75C0000/qup_ssc13_spi_active ) ?�/soc/pinctrl@75C0000/qup_ssc13_spi_sleep + ?�/soc/pinctrl@75C0000/qup_ssc13_uart_active * ?�/soc/pinctrl@75C0000/qup_ssc13_uart_sleep * ?�/soc/pinctrl@75C0000/qup_ssc14_i2c_active ) ?�/soc/pinctrl@75C0000/qup_ssc14_i2c_sleep * ?�/soc/pinctrl@75C0000/qup_ssc14_i3c_active ) @/soc/pinctrl@75C0000/qup_ssc14_i3c_sleep . @%/soc/pinctrl@75C0000/qup_ssc14_i3c_ibi_active - @>/soc/pinctrl@75C0000/qup_ssc14_i3c_ibi_sleep @V/soc/timetick/timer@68a2000 @b/soc/timetick/timer@68a3000 @n/soc/spmi_bus@c400000/pmk8550@0 9 @t/soc/spmi_bus@c400000/pmk8550@0/spmi-vadc@92/therm_table @�/soc/funnel@10041000 @�/soc/funnel@10B04000 @�/soc/funnel@10B44000 @�/soc/funnel@10B50000 @�/soc/tpda@10B47000 @�/soc/tpda@10B53000 @�/soc/tpda@10B55000 �/soc/tnoc@10B31000 9 @�/soc/kernel_test_devices@0/interrupt-controller@10140000 @�/soc/systemcache@24800000 @�/soc/ibi_ssc_0_cfg@7500000 @�/soc/ibi_ssc_1_cfg@7510000 @�/soc/ibi_ssc_2_cfg@7520000 @�/soc/ibi_ssc_3_cfg@7530000 A/soc/ibi_ssc_4_cfg@7540000 A/soc/ibi_ssc_5_cfg@7550000 A"/soc/ibi_ssc_6_cfg@7560000 A0/soc/ibi_ssc_7_cfg@7570000 A>/soc/ibi_ssc_8_cfg@7580000 AL/soc/ibi_ssc_9_cfg@7590000
AZ/soc/vdd_mxa
Ab/soc/vdd_mxc Aj/soc/vdd_cx Aq/soc/vdd_lpi_mx A|/soc/vdd_lpi_cx A�/sw model compatible #address-cells #size-cells spmi-bus0 spmi-bus1 phandle reg reg-names #clock-cells host remote-host fifo-size mtu-size irq-out qos-max-rate channel-name remote-ss mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport ch-name options priority stack-size intents tx-channel rx-channel host-id fflags max-entries dest proc irq core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets ngpios width version egpio gpio-controller #gpio-cells mux config qcom,sleep-config timer-name timer-freq timer-num timer-interrupt use-interrupt sid mid pmic bid therm-tbl label hw-ch hw-settle avg-sp dec-ratio cal-method scaling offset scale-fcn pull-up asid int-table pmic-sid gpio-num arr_id hw-common-params adctm-hw-params trip-range base_port num_ports atid sync_period lpi_funnel lpi_funnel_port port_stm port_lpi_etm port_lpi_stm port_lpi_tpda port_rscc_tpda port_audio_tpda port_sdc_etm port_sdc_itm port_lpi_noc port_aon_cam_noc port_aoc port_ddr_lpi_tnoc dbg_regs pwrdbg_ctrl_reg cti_channels cti_triggers tpdm_name tpda_port dataset cmb_size tpda_name port_occupied_mask tpda_funnel_name tnoc_id tnoc_funnel_name cti_name interrupt-parent interrupt-controller #interrupt-cells message interrupts interrupt-names llcc-common-reg disable-wrsc-on-preload scid core_base_addr ibi_wrapper_base_addr ibi_id gpii gpii_irq mgr_irq od_type status num_qup gsi_pa tcsr_irq gpii_interrupts active clock-names clocks qup_id common_base_addr se_wrapper_base_addr core_frequency qup_flags num_se core_offset ibi_data se_flags se_index FIFO_MODE protocol_supported interface_supported gpi_index num_gpi_index ring_size_multiplier core_irq pdc_irq gpio_int_num SE_EXCLUSIVE pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 gpi_idx num_gpi_idx i2c_hub qup_base common_offset core_freq_hz load_fw ibi_base protocol se_island_config tre_list_size ibi_se_index se_mode dfs_mode ibi_hw_enabled uStructVer pszInstName uaMasterEA pszHwioBase uHwioBaseOffset uHwioBase hBamDev uIntId uBamIntId uMyEE smbus_clk smbus_data uGpioIntNum uaNumEndPoints uaVoltageVote bIsLpiTlmm LA uaEA uDataLineMask num_device_props tlmm_name_str svs_npa_str is_master default_clock_gear prog_bam_trust island_vote subsystem_sleep_vote tlmm_offset tlmm_val svs_npa use_gpio_int log_level no_retention num_local_ports local_port_base local_channel_base shared_channel_base num_local_counters is_lpm_used_for_mgr_bam_trans lpm_mgr_sb_region_base lpm_mgr_sb_region_size is_lpm_sat_sb_region_dump_enable lpm_sat_sb_region_base lpm_sat_sb_region_size ee_assign rev MmpmCoreIdType MmpmCoreInstanceIdType pClientName pwrCtrlFlag callBackFlag MMPM_Callback cbFcnStackSize regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint16 test_uint32 test_uint32_list test_uint64 test_string test_uint8 test_uint8_list_empty test_uint16_list test_uint16_list_empty test_uint32_list_empty test_uint64_list test_uint64_list_empty reg_alt PD_indicator test_oem_entry jeita-alg afp-cold-degc jeita-hard-cold-degc jeita-hard-hot-degc jeita-hard-hys-degc afp-hot-degc vflt-nominal-mv fcc-nominal-ma die-temp-cfg conn-temp-cfg en-aged-batt-comp rechg-iterm rechg-soc-delta-pct rechg-delta-vflt-mv vflt-comp-mv iterm-comp-ma en-wls wls-pre-regulator boost-src otg-boost-src wls-tx-cfg ext-gpio-boost usb-switch wls-load-switch en-apsd-pwr qc-det-cfg dam-hc-override apsd-rerun-cfg dam-aicl-cfg en-ufcs en-dam-qc-usb instance slave-addr force-eoc-5v ptm-cfg-1s se-idx se-int-num se-flags tlmm-gpio-num pmic-gpio-num pmic-idx ufcs-flags snk-max-mv snk-max-ma vdm-limit-cfg wd-timer-cfg-ms wd-timer-pet-ms hw-version sw-version en-chg-lmt charge-end-threshold charge-start-threshold smb-intf-cfg i2c-instance smb-m-addr smb-s-addr smb-r-addr struct-ver plat-id is-test-mode test-mode-flag chg-heartbeat-timer-ms dischg-heartbeat-timer-ms poll-timer-ms chg-done-timer-ms vbatt-avg-sample-size en-linear-soc soc-conv-pt min-linear-soc wd-bark-timer-ms wd-bite-timer-ms gen-test-interface en-stepchg-jeita iterm-ma bmd-src-sel en-beh beh-debug-board beh-normal-batt beh-smart-auth-state beh-unknown-state beh-batt-miss-state beh-invalid-state beh-afp-state dbg-rid-cfg normal-rid-cfg smart-rid-cfg chg-table-max esd-timer-ms esd-voltage-mv esd-init-soc en-batt-auth batt-auth-timeout-s batt-auth-checktimer-ms batt-unauth-charging-action batt-auth-public-key-len batt-auth-challenge-len batt-auth-response-len batt-auth-public-key en-batt-auth-bsi-chip attributes conn-num en-alt-mode bc-ver pd-ver typec-ver op-mode provider consumer dfp-swap-en ufp-swap-en src-swap-en snk-swap-en ext-op-mode port-idx en-pd en-pan pd-rev snk-cap-size snk-caps-pdos snk-max-voltage-mv snk-max-current-ma snk-pwr-eval-alg snk-max-pwr-uw src-max-voltage-mv src-max-current-ma src-max-pwr-uw src-cap-size src-caps-pdos en-pps en-vconn-swap en-fr-swap en-vdm-altmode en-vdm-cable-discovery slow-charge-thr mismatch-thr drp-pps-support mpm-snk-time-ms mpm-src-time-ms pan-ack-tmout-ms batt-cap-vid batt-pid src-cap-ext-cfg en-lpd en-fod rsbu-thr-kohm holdoff-time-ms cooldown-time-s mitigation-current-ma sink-periodic-lpd compbox-imp-cfg-size sbu1-imp-kohm sbu2-imp-kohm cc1-imp-kohm cc2-imp-kohm dp-imp-kohm dm-imp-kohm fod-cc1-imp-kohm fod-cc2-imp-kohm en-snk en-src dam-gpio-en dam-pmic-idx dam-pmic-gpio-num en-dam-src src-rp-val en-audio-adap usb-switch-notify-en vbus-rampdown-wait-ms vbus-default-mv vbus-init-step-mv vconn-src-sel vdo-header cert-state product dfp-product ufp-product sop-discover-resp vph-min-mv fvss-entry-delta-mv fvss-vbatt-filt-tau-us fcss-entry-delta-ma fcss-ibatt-filt-tau-us hold-soc-1-pct cl-learn-min-delta-soc cl-wt-learn soh-tbat-range-degc soh-soc-range ignore-shdn-soc-param pon-debug-fifo-count hpm-fifo-len vbatt-empty-1s vbatt-empty-2s en-split-profile seperate-2p-batt vbat-cut-off-mv ibatt-cutoff-min-ma rconn-mohm ibatt-full-delta-ma image_idx eic_crash_enable eic_crash_type eic_crash_delay pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_binary_local_path pd_binary_remote_path pd_name pd_mon_install_attr pd_mon_image_sw_id subdomain_name pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable image_id service_id instance_id qdss_service_id pram_name pt_name wdog_irq_num err_irq_num code_ram_addr data_ram_addr code_ram_size data_ram_size pram_addr ssc_sdc_physpool_addr ssc_sdc_physpool_size ipcmem_physpool_addr ipcmem_physpool_size diag_cmd_request_f diag_start_stress_test_f diag_stress_test_loopback diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_flow_control_count_base diag_dsm_chained_count_base diag_get_cmd_reg_tbl diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_stress_test_delayed_rsp diag_drop_threshold_config diag_query_enable diag_get_time_api diag_get_drop_per diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_drop_flow_cnt_incr diag_drop_per_step_max diag_drop_per_threshold_max diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version GlbCtxtHWMutexNumber THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks min clientNum routes hw_instance masterIcbPort slaveIcbPort index0 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 llccs scid-mapping-reg clients dump-pools gcc lpass_aon_cc lpass_aon_mx_cc lpass_audio_cc lpass_core_cc lpass_lpmla_cc scc lpass_cesta tlmm qup2_se0_l0 ibi_i3c_qup2_se0_sda qup2_se0_l1 ibi_i3c_qup2_se0_scl qup2_se0_l2 qup2_se0_l3 qup2_se1_l0 ibi_i3c_qup2_se1_sda qup2_se1_l1 ibi_i3c_qup2_se1_scl qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 ibi_i3c_qup2_se2_sda qup2_se2_l1 ibi_i3c_qup2_se2_scl qup2_se2_l2 qup2_se3_l0 ibi_i3c_qup2_se3_sda qup2_se2_l6 qup2_se3_l1 ibi_i3c_qup2_se3_scl qup2_se2_l4 qup2_se3_l2 qup2_se2_l3 qup2_se3_l3 qup2_se2_l5 qup2_se4_l0 qup2_se4_l1 qup2_se4_l2 qup2_se4_l3 qup2_se5_l0 qup2_se5_l1 qup2_se5_l2 qup2_se5_l3 qup2_se5_l6 qup2_se6_l0 qup2_se6_l1 qup2_se6_l2 qup2_se6_l3 qup2_se7_l0 ibi_i3c_qup2_se7_sda qup2_se7_l1 ibi_i3c_qup2_se7_scl qup2_se7_l2 qup2_se7_l3 qup1_se0_l0 ibi_i3c_qup1_se0_sda qup1_se0_l1 ibi_i3c_qup1_se0_scl qup1_se0_l2 qup1_se0_l3 qup1_se1_l0 ibi_i3c_qup1_se1_sda qup1_se1_l1 ibi_i3c_qup1_se1_scl qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se4_l0 ibi_i3c_qup1_se4_sda qup1_se4_l1 ibi_i3c_qup1_se4_scl qup1_se4_l2 qup1_se4_l3 qup1_se5_l0 qup1_se5_l1 qup1_se5_l2 qup1_se5_l3 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup1_se7_l0 qup1_se7_l1 qup1_se7_l2 qup1_se7_l3 qup1_se2_l4 qup1_se2_l5 qup1_se2_l6 top_qup1_se0_i2c_active top_qup1_se0_i2c_sleep top_qup1_se0_spi_active top_qup1_se0_spi_sleep top_qup1_se0_uart_active top_qup1_se0_uart_sleep top_qup1_se1_i2c_active top_qup1_se1_i2c_sleep top_qup1_se1_spi_active top_qup1_se1_spi_sleep top_qup1_se1_uart_active top_qup1_se1_uart_sleep top_qup1_se2_i2c_active top_qup1_se2_i2c_sleep top_qup1_se2_spi_active top_qup1_se2_spi_sleep top_qup1_se2_uart_active top_qup1_se2_uart_sleep top_qup1_se3_i2c_active top_qup1_se3_i2c_sleep top_qup1_se3_spi_active top_qup1_se3_spi_sleep top_qup1_se3_uart_active top_qup1_se3_uart_sleep top_qup1_se4_i2c_active top_qup1_se4_i2c_sleep top_qup1_se4_spi_active top_qup1_se4_spi_sleep top_qup1_se4_uart_active top_qup1_se4_uart_sleep top_qup1_se5_i2c_active top_qup1_se5_i2c_sleep top_qup1_se5_spi_active top_qup1_se5_spi_sleep top_qup1_se5_uart_active top_qup1_se5_uart_sleep top_qup1_se6_i2c_active top_qup1_se6_i2c_sleep top_qup1_se6_spi_active top_qup1_se6_spi_sleep top_qup1_se6_uart_active top_qup1_se6_uart_sleep top_qup1_se7_i2c_active top_qup1_se7_i2c_sleep top_qup1_se7_spi_active top_qup1_se7_spi_sleep top_qup1_se7_uart_active top_qup1_se7_uart_sleep top_qup2_se0_i2c_active top_qup2_se0_i2c_sleep top_qup2_se0_spi_active top_qup2_se0_spi_sleep top_qup2_se0_uart_active top_qup2_se0_uart_sleep top_qup2_se1_i2c_active top_qup2_se1_i2c_sleep top_qup2_se1_spi_active top_qup2_se1_spi_sleep top_qup2_se1_uart_active top_qup2_se1_uart_sleep top_qup2_se2_i2c_active top_qup2_se2_i2c_sleep top_qup2_se2_spi_active top_qup2_se2_spi_sleep top_qup2_se2_uart_active top_qup2_se2_uart_sleep top_qup2_se3_i2c_active top_qup2_se3_i2c_sleep top_qup2_se3_spi_active top_qup2_se3_spi_sleep top_qup2_se3_uart_active top_qup2_se3_uart_sleep top_qup2_se4_i2c_active top_qup2_se4_i2c_sleep top_qup2_se4_spi_active top_qup2_se4_spi_sleep top_qup2_se4_uart_active top_qup2_se4_uart_sleep top_qup2_se5_i2c_active top_qup2_se5_i2c_sleep top_qup2_se5_spi_active top_qup2_se5_spi_sleep top_qup2_se5_uart_active top_qup2_se5_uart_sleep top_qup2_se6_i2c_active top_qup2_se6_i2c_sleep top_qup2_se6_spi_active top_qup2_se6_spi_sleep top_qup2_se6_uart_active top_qup2_se6_uart_sleep top_qup2_se7_i2c_active top_qup2_se7_i2c_sleep top_qup2_se7_spi_active top_qup2_se7_spi_sleep top_qup2_se7_uart_active top_qup2_se7_uart_sleep lpi_tlmm slimbus_clk slimbus_data slimbus_default_gpio_cfg ssc_tlmm ssc_qupv3_se0_0 ssc_qupv3_se0_1 ssc_qupv3_se1_0 ssc_qupv3_se1_1 ssc_qupv3_se2_0 ssc_qupv3_se2_1 ssc_qupv3_se2_2 ssc_qupv3_se4_4 ssc_qupv3_se2_3 ssc_qupv3_se4_5 ssc_qupv3_se3_0 ssc_qupv3_se2_4 ssc_qupv3_se3_1 ssc_qupv3_se2_5 ssc_qupv3_se4_0 ssc_qupv3_se4_1 ssc_qupv3_se4_2 ssc_qupv3_se4_3 ssc_qupv3_se5_2 ssc_qupv3_se5_0 ssc_qupv3_se1_2 ssc_qupv3_se5_3 ssc_qupv3_se5_1 ssc_qupv3_se1_3 ssc_qupv3_se6_0 ssc_qupv3_se6_2 ssc_qupv3_se10_2 ssc_qupv3_se6_1 ssc_qupv3_se6_3 ssc_qupv3_se10_3 ssc_qupv3_se7_2 ssc_qupv3_se7_0 ssc_qupv3_se7_3 ssc_qupv3_se7_1 ssc_qupv3_se8_0 ssc_qupv3_se8_1 ssc_qupv3_se9_0 ssc_qupv3_se9_1 ssc_qupv3_se10_0 ssc_qupv3_se10_1 ssc_qupv3_se11_0 ssc_qupv3_se11_1 ssc_qupv3_se11_2 ssc_qupv3_se11_3 ssc_qupv3_se12_0 ssc_qupv3_se12_1 ssc_qupv3_se13_0 ssc_qupv3_se13_1 ssc_qupv3_se13_2 ssc_qupv3_se13_3 ssc_qupv3_se14_0 ssc_qupv3_se14_1 qup_ssc0_i2c_active qup_ssc0_i2c_sleep qup_ssc0_i3c_active qup_ssc0_i3c_sleep qup_ssc0_i3c_ibi_active qup_ssc0_i3c_ibi_sleep qup_ssc1_i2c_active qup_ssc1_i2c_sleep qup_ssc1_i3c_active qup_ssc1_i3c_sleep qup_ssc1_i3c_ibi_active qup_ssc1_i3c_ibi_sleep qup_ssc1_spi_active qup_ssc1_spi_sleep qup_ssc1_uart_active qup_ssc1_uart_sleep qup_ssc2_i2c_active qup_ssc2_i2c_sleep qup_ssc2_i3c_active qup_ssc2_i3c_sleep qup_ssc2_i3c_ibi_active qup_ssc2_i3c_ibi_sleep qup_ssc2_spi_active qup_ssc2_spi_sleep qup_ssc2_uart_active qup_ssc2_uart_sleep qup_ssc3_i2c_active qup_ssc3_i2c_sleep qup_ssc3_i3c_active qup_ssc3_i3c_sleep qup_ssc3_i3c_ibi_active qup_ssc3_i3c_ibi_sleep qup_ssc4_i2c_active qup_ssc4_i2c_sleep qup_ssc4_spi_active qup_ssc4_spi_sleep qup_ssc4_uart_active qup_ssc4_uart_sleep qup_ssc5_i2c_active qup_ssc5_i2c_sleep qup_ssc5_i3c_active qup_ssc5_i3c_sleep qup_ssc5_i3c_ibi_active qup_ssc5_i3c_ibi_sleep qup_ssc5_uart_active qup_ssc5_uart_sleep qup_ssc6_i2c_active qup_ssc6_i2c_sleep qup_ssc6_i3c_active qup_ssc6_i3c_sleep qup_ssc6_i3c_ibi_active qup_ssc6_i3c_ibi_sleep qup_ssc6_uart_active qup_ssc6_uart_sleep qup_ssc7_i2c_active qup_ssc7_i2c_sleep qup_ssc7_uart_active qup_ssc7_uart_sleep qup_ssc8_i2c_active qup_ssc8_i2c_sleep qup_ssc8_i3c_active qup_ssc8_i3c_sleep qup_ssc8_i3c_ibi_active qup_ssc8_i3c_ibi_sleep qup_ssc9_i2c_active qup_ssc9_i2c_sleep qup_ssc9_i3c_active qup_ssc9_i3c_sleep qup_ssc9_i3c_ibi_active qup_ssc9_i3c_ibi_sleep qup_ssc10_i2c_active qup_ssc10_i2c_sleep qup_ssc10_spi_active qup_ssc10_spi_sleep qup_ssc10_uart_active qup_ssc10_uart_sleep qup_ssc11_i2c_active qup_ssc11_i2c_sleep qup_ssc11_spi_active qup_ssc11_spi_sleep qup_ssc11_uart_active qup_ssc11_uart_sleep qup_ssc12_i2c_active qup_ssc12_i2c_sleep qup_ssc13_i2c_active qup_ssc13_i2c_sleep qup_ssc13_i3c_active qup_ssc13_i3c_sleep qup_ssc13_i3c_ibi_active qup_ssc13_i3c_ibi_sleep qup_ssc13_spi_active qup_ssc13_spi_sleep qup_ssc13_uart_active qup_ssc13_uart_sleep qup_ssc14_i2c_active qup_ssc14_i2c_sleep qup_ssc14_i3c_active qup_ssc14_i3c_sleep qup_ssc14_i3c_ibi_active qup_ssc14_i3c_ibi_sleep SystemTimer WakeUpTimer pmic0 therm_table in_fun0 swao_fun lpi_fun0 lpi_fun1 lpass lpi_rscc lpi_audio intc systemcache0 ibi_ssc_0_cfg ibi_ssc_1_cfg ibi_ssc_2_cfg ibi_ssc_3_cfg ibi_ssc_4_cfg ibi_ssc_5_cfg ibi_ssc_6_cfg ibi_ssc_7_cfg ibi_ssc_8_cfg ibi_ssc_9_cfg vdd_mxa vdd_mxc vdd_cx vdd_lpi_mx vdd_lpi_cx sw �
�� 8 � ( R x qcom,pakala qcom,pakala soc , sw , core cpt_boot_test PD_Access_control 4 W OEM_Flavor_Validation A debugtools tms_diag qcom,tms_diag P � eic qcom,eic Y j y Z version_tbl qcom,image_version_tbl_idx � mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config � � # power qdsp_pm pd qcom,pd-charger-process � diag qcom,charger_user_diagcfg diagcfg_cmd � w � x � = � .P IW b { diagcfg_param � � � � � � � � 1 2 E � [ x � � � � � � � - __symbols__ K/soc O/sw model compatible #address-cells #size-cells phandle PD_indicator test_oem_entry image_id eic_crash_enable eic_crash_type eic_crash_delay image_idx service_id instance_id QDI_QDSP_PM_USER_ID diag_test_cmd_f diag_v2_test_cmd_f diag_legacy_health_count_base diag_ulogdiag_processor_id diag_subsys_id_base diag_lsm_cmd_reg_test_base diag_get_set_drain_param diag_f3_trace_set_config diag_health_stats_base diag_err_ulog_size diag_debug_ulog_size diag_qdss_ulog_size diag_logtracker_ulog_size diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_event_send_max diag_multipd_buf_size diag_multipd_event_heap_size diag_send_buf_size_data_userpd diag_lsm_stack_size diag_stress_task_sleep_complete diag_deferrable_timer diag_deferrable_timer_ex diag_msg_fmt_str_arg_size diag_uimage_mpd_buf_size diag_uimage_f3_trace_buf_size soc sw �
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